[kicad-users] Gross error not caught by DRC (or LVS??)

[Doug McKnight [e-mail] [kicad-users]]

Hello,
I'm still new to Kicad (but not to other types of EDA).
I made a mistake in a PCB layout that caused a gross error but which was, apparently, ignored in the DRC check. Perhaps I misunderstand the scope of DRC, and in particular how much LVS checking it does?
What I did was to, accidentally, put some text on a copper layer that would have shorted some traces together had the board gone to fab.
I noticed the error, but what surprised me was that DRC didn't complain about it. I guess I assumed that DRC was also doing a Layout-versus-Schematic check when it runs, but it can't be doing this in the way I expected.
Should this error have been caught?  If not, it seems to me that other techniques need to be used to prevent or find this type of error. 
Regards,Doug

[[e-mail] [kicad-users]]

When I worked for a medium sized company with in house layout people, they told me to add *everything* to the schematic that was expected to appear on the PCB. This would include text, mounting holes, etc.

I don't know how kicad would handle text in a design rule check, but it is reasonable that if text on a copper layer were part of a net or a part itself, it might throw a flag if it were too close to anything else including traces.

Rick C.

[Pedro Martin [e-mail] [kicad-users]]

Hi Doug,

I have made a test on one of my projects.
I added a copper text over a footprint, making a short with all the pads.

The DRC catched every short-cut. It worked OK.

Regards,
Pedro.

Post by Doug McKnight ***@yahoo.com [kicad-users]
Hello,
I'm still new to Kicad (but not to other types of EDA).
I made a mistake in a PCB layout that caused a gross error but which
was, apparently, ignored in the DRC check. Perhaps I misunderstand the
scope of DRC, and in particular how much LVS checking it does?
What I did was to, accidentally, put some text on a copper layer that
would have shorted some traces together had the board gone to fab.
I noticed the error, but what surprised me was that DRC didn't complain
about it. I guess I assumed that DRC was also doing a
Layout-versus-Schematic check when it runs, but it can't be doing this
in the way I expected.
Should this error have been caught? If not, it seems to me that other
techniques need to be used to prevent or find this type of error.
Regards,
Doug

[Doug McKnight [e-mail] [kicad-users]]

Hi Pedro, Can you please try that not over a footprint, but just somewhere else on the board?  It seems I can reproduce this easily.Thank you.Doug

From: "Pedro Martin ***@yahoo.es [kicad-users]" <kicad-***@yahoogroups.com>
To: kicad-***@yahoogroups.com
Sent: Monday, March 6, 2017 5:45 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)

  Hi Doug,

I have made a test on one of my projects.
I added a copper text over a footprint, making a short with all the pads.

The DRC catched every short-cut. It worked OK.

Regards,
Pedro.

Post by Doug McKnight ***@yahoo.com [kicad-users]
Hello,
I'm still new to Kicad (but not to other types of EDA).
I made a mistake in a PCB layout that caused a gross error but which
was, apparently, ignored in the DRC check. Perhaps I misunderstand the
scope of DRC, and in particular how much LVS checking it does?
What I did was to, accidentally, put some text on a copper layer that
would have shorted some traces together had the board gone to fab.
I noticed the error, but what surprised me was that DRC didn't complain
about it. I guess I assumed that DRC was also doing a
Layout-versus-Schematic check when it runs, but it can't be doing this
in the way I expected.
Should this error have been caught? If not, it seems to me that other
techniques need to be used to prevent or find this type of error.
Regards,
Doug

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[Ray MØDHP [e-mail] [kicad-users]]

Hi Doug

I've tried some F.cu text with a character shorting two tracks (not near a footprint). DRC reports errors.

I also get an error if the character is just touching one of the tracks.

The error is type 42 "track inside a text".

What OS and KiCad version are you using? I'm on Ubuntu 16.04 and the nightly KiCad build.

Cheers

Ray



On 6 Mar 2017, at 14:56, Doug McKnight ***@yahoo.com<mailto:***@yahoo.com> [kicad-users] <kicad-***@yahoogroups.com<mailto:kicad-***@yahoogroups.com>> wrote:



Hi Pedro,
Can you please try that not over a footprint, but just somewhere else on the board?
It seems I can reproduce this easily.
Thank you.
Doug


________________________________
From: "Pedro Martin ***@yahoo.es<mailto:***@yahoo.es> [kicad-users]" <kicad-***@yahoogroups.com<mailto:kicad-***@yahoogroups.com>>
To: kicad-***@yahoogroups.com<mailto:kicad-***@yahoogroups.com>
Sent: Monday, March 6, 2017 5:45 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)


Hi Doug,

I have made a test on one of my projects.
I added a copper text over a footprint, making a short with all the pads.

The DRC catched every short-cut. It worked OK.

Regards,
Pedro.

Post by Doug McKnight ***@yahoo.com [kicad-users]
Hello,
I'm still new to Kicad (but not to other types of EDA).
I made a mistake in a PCB layout that caused a gross error but which
was, apparently, ignored in the DRC check. Perhaps I misunderstand the
scope of DRC, and in particular how much LVS checking it does?
What I did was to, accidentally, put some text on a copper layer that
would have shorted some traces together had the board gone to fab.
I noticed the error, but what surprised me was that DRC didn't complain
about it. I guess I assumed that DRC was also doing a
Layout-versus-Schematic check when it runs, but it can't be doing this
in the way I expected.
Should this error have been caught? If not, it seems to me that other
techniques need to be used to prevent or find this type of error.
Regards,
Doug

[Doug McKnight [e-mail] [kicad-users]]

Hi Ray,
Thanks for the reply. Your comment was helpful. It was simply a case of me misinterpreting the DRC error due, in part, to the indicator arrows pointing at something quite far away from where the actual error was...
Still learning...
Doug


From: "Ray MØDHP ***@outlook.com [kicad-users]" <kicad-***@yahoogroups.com>
To: "kicad-***@yahoogroups.com" <kicad-***@yahoogroups.com>
Sent: Monday, March 6, 2017 8:16 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)

  Hi Doug
I've tried some F.cu text with a character shorting two tracks (not near a footprint). DRC reports errors.
I also get an error if the character is just touching one of the tracks.
The error is type 42 "track inside a text".
What OS and KiCad version are you using? I'm on Ubuntu 16.04 and the nightly KiCad build.
Cheers 
Ray


On 6 Mar 2017, at 14:56, Doug McKnight ***@yahoo.com [kicad-users] <kicad-***@yahoogroups.com> wrote:


 Hi Pedro, Can you please try that not over a footprint, but just somewhere else on the board?  It seems I can reproduce this easily.Thank you.Doug

From: "Pedro Martin ***@yahoo.es [kicad-users]" <kicad-***@yahoogroups.com>
To: kicad-***@yahoogroups.com
Sent: Monday, March 6, 2017 5:45 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)

 Hi Doug,

I have made a test on one of my projects.
I added a copper text over a footprint, making a short with all the pads.

The DRC catched every short-cut. It worked OK.

Regards,
Pedro.

Post by Doug McKnight ***@yahoo.com [kicad-users]
Hello,
I'm still new to Kicad (but not to other types of EDA).
I made a mistake in a PCB layout that caused a gross error but which
was, apparently, ignored in the DRC check. Perhaps I misunderstand the
scope of DRC, and in particular how much LVS checking it does?
What I did was to, accidentally, put some text on a copper layer that
would have shorted some traces together had the board gone to fab.
I noticed the error, but what surprised me was that DRC didn't complain
about it. I guess I assumed that DRC was also doing a
Layout-versus-Schematic check when it runs, but it can't be doing this
in the way I expected.
Should this error have been caught? If not, it seems to me that other
techniques need to be used to prevent or find this type of error.
Regards,
Doug

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[[e-mail] [kicad-users]]

Yep, I am also learning KiCad (and also not new to other tools), and I am having trouble interpreting the DRC results - as you say, it points and describes something that is somewhere else. Glad you found the other problem, I'll keep an eye out for that one myself.
dan

[Cirilo Bernardo [e-mail] [kicad-users]]

Don't worry - you can always move graphical line segments, arcs, andcircles to the copper layer if you really want to short things. These arestill invisible to DRC. The text issue was fixed quite a few months ago.
- Cirilo

From: "Doug McKnight ***@yahoo.com [kicad-users]" <kicad-***@yahoogroups.com>
To: "Ray MØDHP ***@outlook.com [kicad-users]" <kicad-***@yahoogroups.com>
Sent: Tuesday, March 7, 2017 3:22 AM
Subject: False alarm... (was Re: [kicad-users] Gross error not caught by DRC (or LVS??))

  Hi Ray,
Thanks for the reply. Your comment was helpful. It was simply a case of me misinterpreting the DRC error due, in part, to the indicator arrows pointing at something quite far away from where the actual error was...
Still learning...
Doug


From: "Ray MØDHP ***@outlook.com [kicad-users]" <kicad-***@yahoogroups.com>
To: "kicad-***@yahoogroups.com" <kicad-***@yahoogroups.com>
Sent: Monday, March 6, 2017 8:16 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)

  Hi Doug
I've tried some F.cu text with a character shorting two tracks (not near a footprint). DRC reports errors.
I also get an error if the character is just touching one of the tracks.
The error is type 42 "track inside a text".
What OS and KiCad version are you using? I'm on Ubuntu 16.04 and the nightly KiCad build.
Cheers 
Ray


On 6 Mar 2017, at 14:56, Doug McKnight ***@yahoo.com [kicad-users] <kicad-***@yahoogroups.com> wrote:


 Hi Pedro, Can you please try that not over a footprint, but just somewhere else on the board?  It seems I can reproduce this easily.Thank you.Doug

From: "Pedro Martin ***@yahoo.es [kicad-users]" <kicad-***@yahoogroups.com>
To: kicad-***@yahoogroups.com
Sent: Monday, March 6, 2017 5:45 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)

 Hi Doug,

I have made a test on one of my projects.
I added a copper text over a footprint, making a short with all the pads.

The DRC catched every short-cut. It worked OK.

Regards,
Pedro.

Post by Doug McKnight ***@yahoo.com [kicad-users]
Hello,
I'm still new to Kicad (but not to other types of EDA).
I made a mistake in a PCB layout that caused a gross error but which
was, apparently, ignored in the DRC check. Perhaps I misunderstand the
scope of DRC, and in particular how much LVS checking it does?
What I did was to, accidentally, put some text on a copper layer that
would have shorted some traces together had the board gone to fab.
I noticed the error, but what surprised me was that DRC didn't complain
about it. I guess I assumed that DRC was also doing a
Layout-versus-Schematic check when it runs, but it can't be doing this
in the way I expected.
Should this error have been caught? If not, it seems to me that other
techniques need to be used to prevent or find this type of error.
Regards,
Doug

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[Doug McKnight [e-mail] [kicad-users]]

Thanks, that's, er, reassuring....
I'm understanding from this discussion that DRC doesn't look at *all* the actual copper, right?  It makes assumptions that are not unreasonable, but seem to leave a significant hole for the unwary to fall through...
Is there a way to extract the netlist from the actual final gerbers, for example, and do a comparison with the schematic? How do the Kicad experts ensure that there isn't a problem lurking somewhere?
Doug

From: "Cirilo Bernardo ***@yahoo.com [kicad-users]" <kicad-***@yahoogroups.com>
To: "kicad-***@yahoogroups.com" <kicad-***@yahoogroups.com>
Sent: Monday, March 6, 2017 2:35 PM
Subject: Re: False alarm... (was Re: [kicad-users] Gross error not caught by DRC (or LVS??))

  Don't worry - you can always move graphical line segments, arcs, andcircles to the copper layer if you really want to short things. These arestill invisible to DRC. The text issue was fixed quite a few months ago.
- Cirilo

From: "Doug McKnight ***@yahoo.com [kicad-users]" <kicad-***@yahoogroups.com>
To: "Ray MØDHP ***@outlook.com [kicad-users]" <kicad-***@yahoogroups.com>
Sent: Tuesday, March 7, 2017 3:22 AM
Subject: False alarm... (was Re: [kicad-users] Gross error not caught by DRC (or LVS??))

  Hi Ray,
Thanks for the reply. Your comment was helpful. It was simply a case of me misinterpreting the DRC error due, in part, to the indicator arrows pointing at something quite far away from where the actual error was...
Still learning...
Doug


From: "Ray MØDHP ***@outlook.com [kicad-users]" <kicad-***@yahoogroups.com>
To: "kicad-***@yahoogroups.com" <kicad-***@yahoogroups.com>
Sent: Monday, March 6, 2017 8:16 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)

  Hi Doug
I've tried some F.cu text with a character shorting two tracks (not near a footprint). DRC reports errors.
I also get an error if the character is just touching one of the tracks.
The error is type 42 "track inside a text".
What OS and KiCad version are you using? I'm on Ubuntu 16.04 and the nightly KiCad build.
Cheers 
Ray


On 6 Mar 2017, at 14:56, Doug McKnight ***@yahoo.com [kicad-users] <kicad-***@yahoogroups.com> wrote:


 Hi Pedro, Can you please try that not over a footprint, but just somewhere else on the board?  It seems I can reproduce this easily.Thank you.Doug

From: "Pedro Martin ***@yahoo.es [kicad-users]" <kicad-***@yahoogroups.com>
To: kicad-***@yahoogroups.com
Sent: Monday, March 6, 2017 5:45 AM
Subject: Re: [kicad-users] Gross error not caught by DRC (or LVS??)

 Hi Doug,

I have made a test on one of my projects.
I added a copper text over a footprint, making a short with all the pads.

The DRC catched every short-cut. It worked OK.

Regards,
Pedro.

Post by Doug McKnight ***@yahoo.com [kicad-users]
Hello,
I'm still new to Kicad (but not to other types of EDA).
I made a mistake in a PCB layout that caused a gross error but which
was, apparently, ignored in the DRC check. Perhaps I misunderstand the
scope of DRC, and in particular how much LVS checking it does?
What I did was to, accidentally, put some text on a copper layer that
would have shorted some traces together had the board gone to fab.
I noticed the error, but what surprised me was that DRC didn't complain
about it. I guess I assumed that DRC was also doing a
Layout-versus-Schematic check when it runs, but it can't be doing this
in the way I expected.
Should this error have been caught? If not, it seems to me that other
techniques need to be used to prevent or find this type of error.
Regards,
Doug

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