FPGA design with KICAD?

Discussion:

Lothar Behrens

2009-05-04 16:55:14 UTC

Hi,

I think, this is not the main intention of KICAD, but as of the
availability of spice samples, is there also a way to use KICAD for
FPGA design?

Say, I would use a sub sheet to enter a group of logic to be placed
into a FPGA (reduced set of symbols only) and a tool that
translates the usual netlist into a VHDL file.

A possible attempt may be supporting the 74XX series of IC's or some
to most of them to be known in a translation tool based
on the netlist. A barrier to the outer circuit (the pins of a FPGA)
would be all these wires, contacting unsupported components,
eg, they could not translated to be in a FPGA design, but in the outer
area.

Using the sub sheet would be a helper in separating FPGA related logic
from the outer area. (I think I could not distinguish between
signals on different sheets in a netlist, thus I don't see the pins
that connects sheets)

While this could be tried with the plain netlist, a netlist in XML
format would be another option to enable various transformations.

Is this possible?

There are other tools available for this, but a first step entry with
KICAD would be fine, as I work on Mac OS X and there are less
EDA tools available (known by me).

Thanks

Lothar

-- | Rapid Prototyping | XSLT Codegeneration | http://www.lollisoft.de
Lothar Behrens
Heinrich-Scheufelen-Platz 2
73252 Lenningen

------------------------------------

Please read the Kicad FAQ in the group files section before posting your question.
Please post your bug reports here. They will be picked up by the creator of Kicad.
Please visit http://www.kicadlib.org for details of how to contribute your symbols/modules to the kicad library.
For building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups Links

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Frank Bennett

2009-05-12 19:09:27 UTC

Permalink

Post by Lothar Behrens
Hi,
I think, this is not the main intention of KICAD, but as of the
availability of spice samples, is there also a way to use KICAD for
FPGA design?
Say, I would use a sub sheet to enter a group of logic to be placed
into a FPGA (reduced set of symbols only) and a tool that
translates the usual netlist into a VHDL file.

A schematic of Xilinx primitives..dump VHDL (ADA like) and become
twice as productive using Verilog (C like). Some good OpenSource
Simulators are: cVer and Icarus with gtkWaves. The FPGA tools accept
Verilog as well as VHDL.

Check out TKGate (http://www.tkgate.org/), the hierarchical
schematic is actually a verilog netlist with the graphical
information included as comments. It also includes a simulator.

EEschema actually does a better job than TKGate with the relation
to pins on a schematic page to the ports on the corresponding
sheet(module). Adding one should automatically produce the other.
(an unfullfilled enhancement request to the TKGate author) With
TKGate one has to enter each redundantly. There is a tool called
SpeedChart which is cool for this but cost $s... or Summit Design,
which I didn't like as well...

EEschema also seems to need some work handling:
bundles (i.e. {cas, ras, cs[1:0], we} ) verses pure
buses - a[15..0] (I would have prefered a[15:0])
both should be allowed in bus rippers and across port
boundaries to realize continuous assignments like:
assign ctrl[2:0] = {cas, ras, we};

TKGate could also include a "comment" on a schematic page
that would be included inline as RTL code, then alternately
an AND2 primitive could include something like:
"code: assign y= a & b;"

One of my ole favorites (before Verilog-A) for a resistor or
module NetAlias(a,a);
inout a;
endmodule

happy HDLing,
Frank Bennett

Post by Lothar Behrens
A possible attempt may be supporting the 74XX series of IC's or some
to most of them to be known in a translation tool based
on the netlist. A barrier to the outer circuit (the pins of a FPGA)
would be all these wires, contacting unsupported components,
eg, they could not translated to be in a FPGA design, but in the outer
area.
Using the sub sheet would be a helper in separating FPGA related logic
from the outer area. (I think I could not distinguish between
signals on different sheets in a netlist, thus I don't see the pins
that connects sheets)
While this could be tried with the plain netlist, a netlist in XML
format would be another option to enable various transformations.
Is this possible?
There are other tools available for this, but a first step entry with
KICAD would be fine, as I work on Mac OS X and there are less
EDA tools available (known by me).
Thanks
Lothar
-- | Rapid Prototyping | XSLT Codegeneration | http://www.lollisoft.de
Lothar Behrens
Heinrich-Scheufelen-Platz 2
73252 Lenningen

------------------------------------

Please read the Kicad FAQ in the group files section before posting your question.
Please post your bug reports here. They will be picked up by the creator of Kicad.
Please visit http://www.kicadlib.org for details of how to contribute your symbols/modules to the kicad library.
For building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups Links

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jmhill.hartford

2010-07-29 16:34:15 UTC

Permalink

Hi Folks;

Just found this thread. I have an interest in making more use KiCad. I already use KiCad for schematics and PC board layout. I have two items on my wishlist.

o Be able to convert a KiCad schematic to a VHDL structural type description of a circuit. This would be helpful for an undergraduate logic circuits course.

I see that the .lib file format includes pin direction information and that the netlist describes connections between pins. Perhaps a utility can be written to produce such a VHDL structural description. What do you think? I can certainly give it a try.

o Be able to convert a part of a schematic to a VHDL structural description. I have students using KiCad to draw schematics which make some use of CPLDs.

In any case, some discussion would be appreciated.

Thanks;
Jonathan

Post by Frank Bennett

A schematic of Xilinx primitives..dump VHDL (ADA like) and become
twice as productive using Verilog (C like). Some good OpenSource
Simulators are: cVer and Icarus with gtkWaves. The FPGA tools accept
Verilog as well as VHDL.
Check out TKGate (http://www.tkgate.org/), the hierarchical
schematic is actually a verilog netlist with the graphical
information included as comments. It also includes a simulator.
EEschema actually does a better job than TKGate with the relation
to pins on a schematic page to the ports on the corresponding
sheet(module). Adding one should automatically produce the other.
(an unfullfilled enhancement request to the TKGate author) With
TKGate one has to enter each redundantly. There is a tool called
SpeedChart which is cool for this but cost $s... or Summit Design,
which I didn't like as well...
bundles (i.e. {cas, ras, cs[1:0], we} ) verses pure
buses - a[15..0] (I would have prefered a[15:0])
both should be allowed in bus rippers and across port
assign ctrl[2:0] = {cas, ras, we};
TKGate could also include a "comment" on a schematic page
that would be included inline as RTL code, then alternately
"code: assign y= a & b;"
One of my ole favorites (before Verilog-A) for a resistor or
module NetAlias(a,a);
inout a;
endmodule
happy HDLing,
Frank Bennett

------------------------------------

Please read the Kicad FAQ in the group files section before posting your question.
Please post your bug reports here. They will be picked up by the creator of Kicad.
Please visit http://www.kicadlib.org for details of how to contribute your symbols/modules to the kicad library.
For building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups Links

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josh_eeg

2010-07-30 11:19:28 UTC

Permalink

xilinx allready has a sch entery thing in their free download after jumping through signup login etc hoops.
It could be used as a reference...

Post by jmhill.hartford
Hi Folks;
Just found this thread. I have an interest in making more use KiCad. I already use KiCad for schematics and PC board layout. I have two items on my wishlist.
o Be able to convert a KiCad schematic to a VHDL structural type description of a circuit. This would be helpful for an undergraduate logic circuits course.
I see that the .lib file format includes pin direction information and that the netlist describes connections between pins. Perhaps a utility can be written to produce such a VHDL structural description. What do you think? I can certainly give it a try.
o Be able to convert a part of a schematic to a VHDL structural description. I have students using KiCad to draw schematics which make some use of CPLDs.
In any case, some discussion would be appreciated.
Thanks;
Jonathan

Post by Frank Bennett

A schematic of Xilinx primitives..dump VHDL (ADA like) and become
twice as productive using Verilog (C like). Some good OpenSource
Simulators are: cVer and Icarus with gtkWaves. The FPGA tools accept
Verilog as well as VHDL.
Check out TKGate (http://www.tkgate.org/), the hierarchical
schematic is actually a verilog netlist with the graphical
information included as comments. It also includes a simulator.
EEschema actually does a better job than TKGate with the relation
to pins on a schematic page to the ports on the corresponding
sheet(module). Adding one should automatically produce the other.
(an unfullfilled enhancement request to the TKGate author) With
TKGate one has to enter each redundantly. There is a tool called
SpeedChart which is cool for this but cost $s... or Summit Design,
which I didn't like as well...
bundles (i.e. {cas, ras, cs[1:0], we} ) verses pure
buses - a[15..0] (I would have prefered a[15:0])
both should be allowed in bus rippers and across port
assign ctrl[2:0] = {cas, ras, we};
TKGate could also include a "comment" on a schematic page
that would be included inline as RTL code, then alternately
"code: assign y= a & b;"
One of my ole favorites (before Verilog-A) for a resistor or
module NetAlias(a,a);
inout a;
endmodule
happy HDLing,
Frank Bennett

------------------------------------

Please read the Kicad FAQ in the group files section before posting your question.
Please post your bug reports here. They will be picked up by the creator of Kicad.
Please visit http://www.kicadlib.org for details of how to contribute your symbols/modules to the kicad library.
For building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups Links

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josh_eeg

2010-07-30 22:58:14 UTC

Permalink

I read quite a lot on tkgate & it seems realy cool for testing but xilinx still seems like the only one that makes something that will compile at least to my understanding the documentation says like verilog so it is close but not compiling. xilinx stuff I may use because it is there and learning another language won't get me the device I want to make any faster & the maple arm3 won't do multi channel blind source seperation on my adc's inputs in real time.

Post by Frank Bennett

A schematic of Xilinx primitives..dump VHDL (ADA like) and become
twice as productive using Verilog (C like). Some good OpenSource
Simulators are: cVer and Icarus with gtkWaves. The FPGA tools accept
Verilog as well as VHDL.
Check out TKGate (http://www.tkgate.org/), the hierarchical
schematic is actually a verilog netlist with the graphical
information included as comments. It also includes a simulator.
EEschema actually does a better job than TKGate with the relation
to pins on a schematic page to the ports on the corresponding
sheet(module). Adding one should automatically produce the other.
(an unfullfilled enhancement request to the TKGate author) With
TKGate one has to enter each redundantly. There is a tool called
SpeedChart which is cool for this but cost $s... or Summit Design,
which I didn't like as well...
bundles (i.e. {cas, ras, cs[1:0], we} ) verses pure
buses - a[15..0] (I would have prefered a[15:0])
both should be allowed in bus rippers and across port
assign ctrl[2:0] = {cas, ras, we};
TKGate could also include a "comment" on a schematic page
that would be included inline as RTL code, then alternately
"code: assign y= a & b;"
One of my ole favorites (before Verilog-A) for a resistor or
module NetAlias(a,a);
inout a;
endmodule
happy HDLing,
Frank Bennett

------------------------------------

Please read the Kicad FAQ in the group files section before posting your question.
Please post your bug reports here. They will be picked up by the creator of Kicad.
Please visit http://www.kicadlib.org for details of how to contribute your symbols/modules to the kicad library.
For building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups Links

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jmhill.hartford

2010-07-31 03:08:53 UTC

Permalink

Hi Josh;

I'm not sure of everything you mention, I wish you the best with your research and use of FPGAs.

I have experience with the Xilinx tools. The VHDL code I've written by hand is largely generic and the Xilinx tools appear happy with straight VHDL, without concern of where the VHDL code came from. Maybe some day I'll get to Verilog.

Jonathan

Post by josh_eeg
I read quite a lot on tkgate & it seems realy cool for testing but xilinx still seems like the only one that makes something that will compile at least to my understanding the documentation says like verilog so it is close but not compiling. xilinx stuff I may use because it is there and learning another language won't get me the device I want to make any faster & the maple arm3 won't do multi channel blind source seperation on my adc's inputs in real time.

Post by Frank Bennett

A schematic of Xilinx primitives..dump VHDL (ADA like) and become
twice as productive using Verilog (C like). Some good OpenSource
Simulators are: cVer and Icarus with gtkWaves. The FPGA tools accept
Verilog as well as VHDL.
Check out TKGate (http://www.tkgate.org/), the hierarchical
schematic is actually a verilog netlist with the graphical
information included as comments. It also includes a simulator.
EEschema actually does a better job than TKGate with the relation
to pins on a schematic page to the ports on the corresponding
sheet(module). Adding one should automatically produce the other.
(an unfullfilled enhancement request to the TKGate author) With
TKGate one has to enter each redundantly. There is a tool called
SpeedChart which is cool for this but cost $s... or Summit Design,
which I didn't like as well...
bundles (i.e. {cas, ras, cs[1:0], we} ) verses pure
buses - a[15..0] (I would have prefered a[15:0])
both should be allowed in bus rippers and across port
assign ctrl[2:0] = {cas, ras, we};
TKGate could also include a "comment" on a schematic page
that would be included inline as RTL code, then alternately
"code: assign y= a & b;"
One of my ole favorites (before Verilog-A) for a resistor or
module NetAlias(a,a);
inout a;
endmodule
happy HDLing,
Frank Bennett

------------------------------------

Please read the Kicad FAQ in the group files section before posting your question.
Please post your bug reports here. They will be picked up by the creator of Kicad.
Please visit http://www.kicadlib.org for details of how to contribute your symbols/modules to the kicad library.
For building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups Links

<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/kicad-users/

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dalescott5952@yahoo.com [kicad-users]

2016-07-30 23:58:20 UTC

Permalink

I use KiCad for general circuit design, and will be starting an FPGA design in a month. In general, I like the idea of creating a top-level schematic with the pads and essentially a top-level block diagram for the FPGA. I will then use VHDL for everything below the level of the block diagram (i.e. there will be a VHDL entity/architecture pair for each block on the top-level schematic).

I hope this workflow will be more efficient than using separate tools because it defines the FPGA pinouts in the same tool as the system level circuit schematic and pcb design, so no "oops, forgot to update that", and also it provides a graphical top-level block diagram of the FPGA for reference and project documentation. I used this method with success for one of the largest 0.8mm gate arrays made many many years ago, and it worked well then (with Mentor Neted and command-line Synopsys v1.0).

I also hope to extract a netlist of the FPGA for functional simulation (which I understand is not available in the free Xilinx tools), and would appreciate any comments on best practice or pitfalls.

Regards,
Dale

gnuarm.2007@arius.com [kicad-users]

2016-07-31 19:52:28 UTC

Permalink

I would discourage you from trying to use schematic for any aspect of FPGA design. I used to do that many, many years ago and it is just simply a PITA while buying you very little. On top of it all, it makes it hard to simulate your full design which is the most important part of your project. I have done FPGA designs where the simulation was done so thoroughly that literally no bugs were found in the FPGA on the board that weren't really specification errors. Do not sell short the importance of good simulation and the test bench which drives it.

I believe the input the synthesis from schematic is EDIF. How exactly do you expect to generate an EDIF file from the schematic? I'm not at all sure how well the simulators will accept EDIF files, but I imagine there must be a way to do that because no one would ever use schematic capture if it wasn't supported by simulation. But I doubt you will be able to drive an EDIF top level file from a VHDL test bench in simulation, not sure as I've never tried it.

The issue of maintaining pin out consistency between tools comes down to generating a new output file from the schematic capture every time a change is made. This has to be done regardless of whether you use a top level FPGA schematic or not. The only difference is whether the file contains preferences to set the pinout or an EDIF file to describe the connectivity.

BTW, there is no need to use any one package over another for simulation. You don't need to use the Xilinx tools to simulate a Xilinx design. You can do that using the Altera or Lattice tools or use one of the open source simulators. Simulation verifies your HDL which won't change between vendors unless you are using proprietary features. There should not be a need to further simulate the placed and routed design unless you feel the synthesis tool is corrupting your design.

I think the biggest problem you will face in using schematic to design FPGAs is the lack of decent support, either from the vendors or from colleagues.

Rick C.

---In kicad-***@yahoogroups.com, <***@...> wrote :

I use KiCad for general circuit design, and will be starting an FPGA design in a month. In general, I like the idea of creating a top-level schematic with the pads and essentially a top-level block diagram for the FPGA. I will then use VHDL for everything below the level of the block diagram (i.e. there will be a VHDL entity/architecture pair for each block on the top-level schematic).

I hope this workflow will be more efficient than using separate tools because it defines the FPGA pinouts in the same tool as the system level circuit schematic and pcb design, so no "oops, forgot to update that", and also it provides a graphical top-level block diagram of the FPGA for reference and project documentation. I used this method with success for one of the largest 0.8mm gate arrays made many many years ago, and it worked well then (with Mentor Neted and command-line Synopsys v1.0).

I also hope to extract a netlist of the FPGA for functional simulation (which I understand is not available in the free Xilinx tools), and would appreciate any comments on best practice or pitfalls.

Regards,
Dale

Patrick Maupin pmaupin@gmail.com [kicad-users]

2016-08-01 03:39:05 UTC

Permalink

I second this. I go the other way, using scripts to match the netlist with
the FPGA top module.

Post by ***@arius.com [kicad-users]
I would discourage you from trying to use schematic for any aspect of FPGA
design. I used to do that many, many years ago and it is just simply a
PITA while buying you very little. On top of it all, it makes it hard to
simulate your full design which is the most important part of your
project. I have done FPGA designs where the simulation was done so
thoroughly that literally no bugs were found in the FPGA on the board that
weren't really specification errors. Do not sell short the importance of
good simulation and the test bench which drives it.
I believe the input the synthesis from schematic is EDIF. How exactly do
you expect to generate an EDIF file from the schematic? I'm not at all
sure how well the simulators will accept EDIF files, but I imagine there
must be a way to do that because no one would ever use schematic capture if
it wasn't supported by simulation. But I doubt you will be able to drive
an EDIF top level file from a VHDL test bench in simulation, not sure as
I've never tried it.
The issue of maintaining pin out consistency between tools comes down to
generating a new output file from the schematic capture every time a change
is made. This has to be done regardless of whether you use a top level
FPGA schematic or not. The only difference is whether the file contains
preferences to set the pinout or an EDIF file to describe the
connectivity.
BTW, there is no need to use any one package over another for simulation.
You don't need to use the Xilinx tools to simulate a Xilinx design. You
can do that using the Altera or Lattice tools or use one of the open source
simulators. Simulation verifies your HDL which won't change between
vendors unless you are using proprietary features. There should not be a
need to further simulate the placed and routed design unless you feel the
synthesis tool is corrupting your design.
I think the biggest problem you will face in using schematic to design
FPGAs is the lack of decent support, either from the vendors or from
colleagues.
Rick C.
I use KiCad for general circuit design, and will be starting an FPGA
design in a month. In general, I like the idea of creating a top-level
schematic with the pads and essentially a top-level block diagram for the
FPGA. I will then use VHDL for everything below the level of the block
diagram (i.e. there will be a VHDL entity/architecture pair for each block
on the top-level schematic).
I hope this workflow will be more efficient than using separate tools
because it defines the FPGA pinouts in the same tool as the system level
circuit schematic and pcb design, so no "oops, forgot to update that", and
also it provides a graphical top-level block diagram of the FPGA for
reference and project documentation. I used this method with success for
one of the largest 0.8mm gate arrays made many many years ago, and it
worked well then (with Mentor Neted and command-line Synopsys v1.0).
I also hope to extract a netlist of the FPGA for functional simulation
(which I understand is not available in the free Xilinx tools), and would
appreciate any comments on best practice or pitfalls.
Regards,
Dale